Design and implementation of complex arithmetic operations using binary logarithmic number system

Now a day´s various real time applications and image processing applications requires hardware that can perform various complex arithmetic operations. These operations can be performed by using binary logarithmic number system. This paper includes binary logarithmic circuit based on FPGA. Above architecture uses combinational logic circuit elements and fixed point data path number format. The architecture is able to calculate the logarithm of integer number, fractional number and integer fractional number. This architecture is designed in Xilinx Virtex-5 device. This architecture consumes minimal FPGA resources that are shown by device utilization summary. Finally error analysis is done which shows that architecture has minimal number of errors considering fractional number and fixed point numbers.