On the improvement of phase noise errors in wireless communication systems

Modern wireless communication systems such as 4G LTE (Long-Term Evolution) are expected to deliver higher data rates. However their performances are heavily impacted by the emergence of Phase noise (PN) in the transceivers. In fact PN has become an integral part of the Frequency Synthesizer design. In the process of generating carrier waves, the local oscillators of the frequency synthesizers generate an unwanted phase noise that limits the performance of the transceivers. Despite several research advances that sought to mitigate and suppress phase noise errors in radio transceivers, phase noise remains a major problem that limits the performance of wireless communication systems. Phase noise is mainly caused by the oscillators´ inability to produce a single and clean frequency without spurious tones and harmonics. In this paper a modified Fractional Phase Locked Loop Frequency Synthesizer (FPLL FS) architecture that is capable of suppressing unwanted spurs is presented. Simulation results show that the proposed model achieves significantly low phase noise level at about -145dBc/Hz with minimal spurious tones in the frequency of interest.