Load-aware stochastic feedback control for DVFS with tight performance guarantee

Dynamic voltage and frequency scaling (DVFS) has become a primary means for achieving power efficiency on many processor architectures. However, traditional DVFS techniques cannot provide tight performance guarantees while scaling the clock frequency. We present an elegant, theoretical approach to stochastically characterize workloads. Based on load characterization, a systematic feedback control design methodology is developed that leads to stochastic minimization of performance loss. It is demonstrated that our load-aware stochastic approach is able to significantly reduce processor power consumption while delivering a performance guarantee that is much tighter than what it is achievable with classical feedback controller.