DocumentCode
3695546
Title
Design and Implementation of IP Core for 1553B bus test
Author
Xiao Liu;Xiaoguang Hu
Author_Institution
State Key Laboratory of Virtual Reality Technology and Systems, Beihang University, Beijing, 100191, China
fYear
2015
fDate
6/1/2015 12:00:00 AM
Firstpage
1608
Lastpage
1612
Abstract
MIL-STD-1553B is an avionics bus which is adopted widely, but the 1553B ASIC is difficult to be reprogrammed and modified. Most 1553B applications currently interface via dedicated protocol chip, such as BU-61580, resulting in inferior flexibility and high spending. In this paper, the architecture, function and realization of IP core for implementing 1553B protocol on field programmable device is discussed. The other important point is to raise the fault injection and error detection design method at the protocol layer of IP core. Finally, the experiment results show that the IP core can accord with communication protocol and realize bus test functionality.
Keywords
"IP networks","Protocols","Synchronization","Decoding","Random access memory","Standards","Encoding"
Publisher
ieee
Conference_Titel
Industrial Electronics and Applications (ICIEA), 2015 IEEE 10th Conference on
Type
conf
DOI
10.1109/ICIEA.2015.7334219
Filename
7334219
Link To Document