• DocumentCode
    3697884
  • Title

    A 103fsrms 1.32mW 50MS/s 1.25MHz bandwidth two-step flash-ΔΣ time-to-digital converter for ADPLL

  • Author

    Ying Wu;Ping Lu;Robert Bogdan Staszewski

  • Author_Institution
    Delft University of Technology, Netherlands
  • fYear
    2015
  • fDate
    5/1/2015 12:00:00 AM
  • Firstpage
    95
  • Lastpage
    98
  • Abstract
    A 50-MS/s two-step flash-ΔΣ time-to-digital converter (TDC) using a 2-channel time-interleaved time-domain register with an implicit adder/subtractor demonstrates a 3rd order noise-shaping. The TDC is fabricated in 40-nm CMOS and consumes 1.2 mA from a 1.1 V supply. At frequencies below 1.25 MHz, the TDC error integrates to 103 fsrms, which is equal to an equivalent resolution of 1.6 ps.
  • Keywords
    "Quantization (signal)","Registers","Bandwidth","Multi-stage noise shaping","Clocks","Discharges (electric)"
  • Publisher
    ieee
  • Conference_Titel
    Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE
  • Type

    conf

  • DOI
    10.1109/RFIC.2015.7337713
  • Filename
    7337713
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3697884