An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects

An electrical and optical concurrent design methodology for enlarging the jitter margin of 25.8-Gb/s optical interconnects is proposed and evaluated. As the key for establishing this design methodology, a simple method for modeling characteristics of a laser diode (LD) (hereafter, "LD modeling method") is adopted. The LD modeling method calculates an optical eye diagram on the basis of measured rising/falling step responses, and the calculated eye diagram agrees well the measured one; namely, the jitter error between them is less than 1.6 ps. Error-free 25.8-Gb/s optical transmission between FPGAs was experimentally demonstrated by optimizing equalization gain of the FPGAs on the basis of the developed design methodology. Moreover, random jitter (RJ) due to relative intensity noise of a LD was reduced by 20% by shortening the transition time of an optical transmitter (TX).