A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS

A DC-to-12.5Gb/s all-rate CDR IC with a single LC VCO is fabricated in 90nm CMOS. Static fractional dividers with an asynchronous phase calibration scheme are employed to generate all-rate clock signals without a phase mismatch or duty cycle distortion. The IC features an automatic loop gain control scheme which adjusts the bandwidth of a CDR automatically in the background for optimum BER performance by monitoring the phase difference between the incoming data and the recovered clock signal. The proposed CDR supports reference-less all-rate operation and compensates for 20dB of channel loss using a CTLE, a one-tap DFE and a three-tap pre-emphasis filter. The power efficiency of the test chip is 4.88mW/Gb/s.