Test-access-mechanism optimization for multi-Vdd SoCs

The use of multiple voltage levels introduces new challenges for testing Multi-V_dd SoCs. Time-Division-Multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the Test-Access-Mechanism (TAM) in the SoC. Single-V_dd TAM optimization techniques consider neither the highly constrained test environment of multi-V_dd SoCs nor the benefits provided by TDM, therefore they are not suitable for multi-V_dd SoCs. In this paper, we propose the first TAM optimization technique for multi-V_dd SoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a Branch-&-Bound approach, it quickly identifies the most effective TAM configurations. Experiments using SoCs from industry highlight the benefits of the proposed technique on multi-V_dd designs, for both single-site and multi-site test applications.