• DocumentCode
    3707855
  • Title

    A two-stage hog feature extraction processor embedded with SVM for pedestrian detection

  • Author

    Xu Yuan;Li Cai-nian;Xu Xiao-liang;Jiang Mei;Zhang Jian-guo

  • Author_Institution
    Shenzhen Key Lab of Advanced Communication and Information Processing College of Information Engineering, Shenzhen University, Shenzhen, 518000, China
  • fYear
    2015
  • Firstpage
    3452
  • Lastpage
    3455
  • Abstract
    A two-stage pipeline architecture for pedestrian detection processor, which embeds the support vector machine (SVM) classifier into the Histogram of Oriented Gradients (HOG) normalization module is proposed. This architecture can effectively reduce hardware resource consumption and can perform pedestrian detection task real-timely. Also, an algorithm is proposed to avoid duplicated detection automatically. The architecture is verified on Spartan-6 FPGA for SVGA resolution video (800×600) at 47 fps/100MHz.
  • Keywords
    "Support vector machines","Histograms","Computer architecture","Pipelines","Hardware","Field programmable gate arrays","Real-time systems"
  • Publisher
    ieee
  • Conference_Titel
    Image Processing (ICIP), 2015 IEEE International Conference on
  • Type

    conf

  • DOI
    10.1109/ICIP.2015.7351445
  • Filename
    7351445
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3707855