Systemic optimization of on-chip thermoelectric cooling

Economic viability of on-package, in-situ cooling based on Thin-film Thermoelectric Coolants (TF-TEC) for hot-spot cooling involves myriad challenges necessitating engineering trade-offs. Principal factors include the cost of integration, the net energy consumption of the TEC based system, as well as system-level complexities arising from issues such as mutual thermal conflicts and interdependencies between the TEC and other package-level entities such as the Thermal grease (TIM), impact on the external convective cooling system, and the number of hot-spots present. In this paper, we examine these challenges both analytically and empirically, and propose a heuristic based method to overcome them. The method forms the basis for a generic optimization framework that enables system-level optimization of on-chip thermoelectric cooling in a commercial microprocessor package. We find a resultant cooling of up to 3°C at TDP delivered per core with a ~11% improvement in energy efficiency.