Scratchpad memory management using data-prefetching

Nowadays, multicore processors including dozens of cores are a reality and the challenge of designing microprocessors with hundreds of cores does not appear far from being achieved. However, some questions remain open, despite the proposals found in the literature. Memory latency, data locality and programmability are some of the more critical ones. As the number of cores in multi-core processor architectures increases, so does the need of more efficient memory hierarchy and resource management scheme. The design of efficient memory hierarchy and memory management policy becomes a very important research subject in multi core architecture field. The usage of resource allocation strategies becomes increasingly necessary. This paper presents the design and implementation of a multi-core node with support to memory configuration and hardware-based scratchpad memory management. The node consists of 9 cores (8 slave cores and a master core) and a configurable local memory. The proposed architecture was implemented with VHDL and prototyped with FPGA development boards. Experimental results show that the proposed hardware-based scratchpad memory management unit can achieve 99,0 of hits in data address prediction and 97,1% of hit when searching data-frames in the local memory.