Study of failures in interconnection wires between basic digital gates

Some of the flaws in the interconnection wires of digital integrated circuits can be caused by fabrication defects or wear as the effect of electromigration effect. Interconnection wires add parasitic effects such as resistances and capacitances which contribute to the propagation delay of a logic gate signal to another. For long length wires the Elmore delay model for RC networks ladder, allows to estimate the propagation delay of a wire ideally without faults, and give a vision of the repercussions in the output signal between two connected inverters with a faulty wire at different points. Therefore, is presented a study of propagation delay in interconnection wire for a TSMC 0.18μm technology.