FPGA implementation of a combined hamming ? AES error tolerant algorithm for on board satellite

LEO satellites operate in a harsh radiation environment and therefore any electronic systems used on-board are very susceptible to faults induced by radiation., This paper presents an algorithm to protect the on board encryption process from Single Event Upsets (SEU). The presented algorithm combines Advanced Encryption Standard (AES)with hamming error detection and correction code. The algorithm is designed using VHDL and targeted to be implemented on a Field Programmable Gate Arrays (FPGA). The simulation results show that the proposed design corrects any single error injected in the data during processing.