DocumentCode
3722851
Title
A Method of Diagnostic Test Generation for Transition Faults
Author
Renji Ono;Satoshi Ohtake
Author_Institution
Grad. Sch. of Eng., Oita Univ., Oita, Japan
fYear
2015
Firstpage
273
Lastpage
278
Abstract
This paper proposes a complete method of diagnostic test generation for transition faults. The method creates a diagnostic test generation model for a pair of transition faults to be distinguished from a given full-scan sequential circuit and employs an ordinary transition fault ATPG tool. The proposed model supports launch-off-capture and launch-off-shift modes which is supported by the ATPG tool. Diagnostic test patterns generated by the proposed method are of the same form as the scan test patterns of the given circuit, i.e., no pattern conversion is necessary. Experimental results show that a commercial transition fault ATPG tool can be utilized in our proposed method using benchmark circuits and, for a given undistinguished pair, the proposed method can generate a test pattern for distinguishing them or prove that they are indistinguishable.
Keywords
"Circuit faults","Automatic test pattern generation","Integrated circuit modeling","Delays","Sequential circuits","Logic gates"
Publisher
ieee
Conference_Titel
Dependable Computing (PRDC), 2015 IEEE 21st Pacific Rim International Symposium on
Type
conf
DOI
10.1109/PRDC.2015.47
Filename
7371871
Link To Document