Accuracy-configurable approximate multiplier with error detection and correction

Real-time multimedia applications which demand very low decoding delays are increasing day-by-day. To address this challenge, in error-resilient applications, many approximate computing architectures for delay critical units have been proposed. In this paper, we propose an architecture for an approximate multiplier, accuracy of which can be configured during the run-time. According to the requirement of the application, the multiplier can be configured to operate in an exact mode or in any of the approximate modes, reducing its decoding delay and the dynamic power consumed. The architecture for the proposed approximate multiplier has been synthesized and simulated using Cadence design tools. Using 16-bit multiplication, it has been demonstrated that, the pass-rate and the propagation delay of the proposed multiplier is comparable or better than most of the published inaccurate multipliers. The proposed approximate multiplier is successfully used in a JPEG conversion application and performances of different accuracy modes are compared.