Design of minimum complexity reversible multiplier

Reversible digital multipliers theoretically do not dissipate energy but are very complex in design. To reduce the gate count, many proposed optimizations employ large reversible gates, which however neither decrease the circuit complexity nor its quantum cost. In this paper, we present design techniques that result in minimal complexity of 4×4-bits unsigned reversible multiplier in terms of the number of gates, the number of garbage outputs, the number of constant inputs and the total quantum cost.