Modified positive feedback adiabatic logic for ultra low power VLSI

In this paper modified positive feedback adiabatic logic (MPFAL). MPFAL is based on positive DC voltage of range 0.1 to 0.45 V. Simulation studies of modified PFAL circuits have been done in Cadence Virtuoso Tool using UMC 180 nm CMOS technology. INVERTER, NAND gate, NOR gate and EX-NOR gate are obtained by this modified technique and this technique is compared with positive feedback adiabatic logic (PFAL). Comparison shows that average power is reduced in case of modified technique compared to PFAL for the input of frequency range 10 to 500 MHz and simulation is carried out by taking 50 to 300 fF ranges of load capacitances. This technique used in ultra-low power digital devices operated at higher frequencies. Number of transistor counts as same as PFAL.