Encryption implementation based on symmetric algorithm using a key rounds upto four rounds

The proposed implementation in this paper describes a new advance encryption architecture. The implementation developed for the purpose of obtaining high performance and achieving efficient utilization area of the field programmable gate array (FPGA) resources. The maximum clock frequency is 134.686 MHz and the number of the uses slices is 394. The design consists of four encryption stages based on xor operand. The design used a single mixcolumn stage in order to reduce the chip area which improves the throughput results. The design model is typically developed by a hardware description language and implemented on Xilinix device class spartan3.