Comparative performance evaluation of address decoding schemes: SRAM design perspective

Static Random Access Memory (SRAM) arrays are widely used as cache memory in microprocessors and Application Specific Integrated Circuits (ASIC´s) and occupy a significant area on the chip. Large arrays of high-speed SRAM help boost the system performance. Address decoding takes nearly two-thirds of the memory access time in SRAMs. The decoder design hugely impacts the system performance and thus should be, high speed, low power consuming and have a small layout area. This paper presents a variety of address decoding schemes and compares them on the basis of area, power and timing. It was observed that Divided Wordline Decoder(DWL) was the fastest decoder with 1.4 times speed of a single stage decoder however, the area is 1.2 times more and 1.05 times additional power dissipation. In terms of power saving, pass transistor based decoder consumes 1.2 times less power and 1.1 times more area. Column based decoding is the best example of an area efficient decoder.