SAT based approach for power on inrush current minimization with power gating

Today low power implementation in the modern system on chips requires a holistic and concurrent approach which includes collaboration between power modeling and software hardware co-design. Power gating is one of the emerging low power design techniques used in all the portable devices. The main goal of power gating is to eliminate the leakage current in standby mode. When the functional unit is powered on, a large and sudden inrush current is prompted through a low resistance path to ground. If this current is excessive, then the produced surge may cause IR voltage drops and electromigration. This has a negative impact on circuit reliability and performance. Therefore an estimation of this maximum current during power up is essential for designing reliable and high performance CMOS combinational circuits. This paper describes important considerations of the high-level synthesis technique on the maximum power on inrush current. Based on this perception, a satisfiability (SAT) based approach is proposed in this paper. The problem of scheduling and functional unit binding is formulated as a satisfiability problem (SAT) and a PB-SAT solver is utilized for discovering the optimal binding solution that minimizes the inrush current at the high level synthesis stage itself in the circuit design process.