Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework

The increased computational power required by modern large-scale computing system is pushing the adoption of heterogeneous components into mainstream. While Graphic Processing Units (GPUs) are frequently adopted as core heterogeneous computational elements, Field Programmable Gate Array (FPGA) based heterogeneous systems are being investigated and adopted due to their claimed superiority in power efficiency. However, the lack of proper approaches and methodologies to systematically push the performance of such devices are among the principal factors limiting the adoption of these devices into mainstream. In this paper, we investigate the adoption of Polyhedral Analysis (PA) to extract data level parallelism from sequential code, defining a methodology for High Level Synthesis (HLS) aimed at FPGA based system. We show how our approach systematically produces speedups proportional to the amount of data level parallelism available in the input programs.