Exploiting hardware abstraction for hybrid parallel computing framework

Dedicated hardware modules on Field-Programmable Gate Arrays (FPGAs) are applied to achieve significant performance improvement over the software implementations. However, even in a simple system-on-chip (SoC) design on FPGA, hardware accelerators are managed explicitly by writing hardware/software interfaces. Programmers have to go through massive details to control and communicate with hardware accelerators, not to mention complicated functions to achieve memory allocation and hardware reuse. Besides, designing hardware accelerators still lacks productivity and flexibility. Promising data-level parallel applications can be accelerated by using recent parallel programming models. In this work, we extend software threads to hardware threads. By implementing a hybrid parallel computing framework the parallel applications are supported through the scheduling and reusing of the threads. Programmers can create software threads in an embedded OS environment without managing hardware details. Hardware manager takes over software threads and manage hardware resources in terms of reallocation and isolation. Experimental results demonstrate that hardware threads can achieve up to 10 times speedup over software implementation. The relationships between the length of scheduling time slices, and the performance and the response time are carefully evaluated. Besides, as the number of threads increases, the system demonstrates a good scalability.