Rethinking manycore caches for scale-out applications

Scale-out applications have become the dominant applications in current data centers. We perform a comprehensive analysis of memory access behavior for these applications. We observe that L2/L3 cache hit rate is relatively low compared with L1 cache. This indicates that there is huge mismatch between the demands of the scale-out applications and existing predominant processor microarchitecture. Based on our observation, we propose ρCache, a cache structure of combining L1D private cache and L1D shared cache for SMT-based manycore processor. The simulation results show that ρCache can significantly save much chip area at the cost of slightly increase of memory access latency.