Keynote 3: "Ensuring robustness in today´s IoT era"

Today´s IoT design teams, use heterogeneous IP blocks from numerous sources in several-levels of hierarchy. To ensure manufacturing quality and filed reliability for such IoTs, DFT designers adopt new test solutions across heterogeneous IP, which is meant to enable concurrent test, power reductions during test, DFT closure, isolated debug and diagnosis, pattern porting, calibration, and uniform access. This tutorial covers hierarchical test trends and solutions based on IEEE test standards, such as IEEE 1500, 1687 and 1149.1, along with intelligent infrastructure IP to help achieve the above advantages. This keynote, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of requirements for robustness. It will also address post-silicon analysis and yield optimization trade-offs using volume diagnostic, and failure coordinate calculation. With the proliferation of IoT, this keynote will cover the infrastructure IP needed to address the above challenges.