Efficient multiply-add unit specified for DSPs utilizing low-power pipeline modulo 2n+1 multiplier

In this work, a new efficient pipeline structure for modulo 2n+1 modified booth multiplier is proposed. Furthermore, the same structure is extended to design new pipeline modulo 2n+1 MAC (Multiply and ACcumulate) unit which is the fundamental part of DSPs (Digital Signal Processors). As DSPs are specifically designed for digital signal processing, they always implement a so-called MAC-instruction. So for improving the performance of DSPs, it is beneficial to improve the efficiency of MAC-instruction. There are three major categories for modulo 2n+1 multipliers but only one of them, which uses weighted representation for one operand and diminished-1 representation for another one, outperforms the other two categories. The proposed MAC unit lies in this category. Pipeline structure along with multi voltage technique enables a trade-off between power consumption and delay. Whenever high-performance with least delay is desirable (e.g. video real-time processing), standard supply voltage could be chosen. Otherwise by reducing supply voltage, power consumption would decrease significantly. Results based on CMOS transistor level implementation for both multiplier and MAC units demonstrate that the proposed pipeline multiplier and MAC units yield significant PDP and power savings.