Flexible data sharing architecture of WiMAX heterogeneous Multiprocessor System on Chip

Heterogeneous Multiprocessor System on Chip (MP-SoC) promises a better computing performance while keeping the dissipation energy low. This feature is very suitable for wireless communication system where the power consumption becomes a vital consideration. This paper presents a new flexible data sharing architecture for WiMAX baseband MPSoC that incorporates Inter Processor Communication (IPC), multi-processors, multi-bus, multi-frequency, and parallel processing design of Medium Access Controller (MAC) layer. This WiMAX MPSoC which is based on RISC processor with multi-bus AMBA system runs in heterogeneous frequency of 40 MHz and 120 MHz. The system has been implemented and verified using Altera Stratix FPGA board. The verification result shows that the system can work in real-time with maximum throughput 11 MBps using only 40 MHz system clock.