Compact model for vertical silicon nanowire based device simulation and circuit design

Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows excellent match with calibrated TCAD at device as well as circuit level for both long and short channel devices. Further, the model results underline the importance of parasitics on nanowire based circuit performance.