Pipelined phase accumulator using han carlson adders and reduced pre-skewing flip-flops for DDFS

This paper presents a 32-bit pipelined Phase Accumulator (PA) design for direct digital frequency synthesizers (DDFSs) in 90nm CMOS technology. The proposed PA not only minimizes the power dissipation but also reduces the number of pre-skewing flip-flops. This is achieved by substituting the pre-skewing registers of the first stage of a previously proposed architecture with low power D-latches. The proposed PA makes use of a specialized parallel prefix adder as part of the 4 bit accumulator subunit. These sub-units are directly fed with the Frequency Control Word (FCW) bit stream via sequential loading scheme generated from gated clocks. A speed of 1.5 GHz is achieved with power consumption reduced by 47% compared to its predecessor.