A two-level fanout system for the CDF silicon vertex tracker

The Fanout system is part of the new trigger processor “Silicon Vertex Tracker” (SVT) dedicated to the reconstruction of charged particle trajectories at the Level 2 of the CDF trigger. The SVT has a maximum event rate of 100 kHz and a latency time of 10 μs. Its core is organised as 12 identical systems (slices) running in parallel almost independently. This implementation of the device derives from the geometry of the Silicon Vertex Detector (SVXII) which is divided in 12 identical wedges along the azimuthal angle. Each SVT slice links the digitized pulse heights found within one SVXII wedge to the tracks reconstructed in the corresponding 30° angular region of the Central Outer Tracker (COT) by the Level 1 Fast Track finder (XFT). Since the COT works as a single entity and the XFT tracks are output on a single data stream, their distribution to the proper SVT slices requires a dedicated Fanout system. This system is a multi-board project running on a common 20 MHz clock, where the fanout function is performed in two steps by one “Fanout A” and two “Fanout B” boards. The architecture, design and implementation of this system are described