Reducing inter-task interference delay by optimizing bank-to-core mapping

Inter-task interferences on the shared resources are the main difficulty in analyzing the timing behavior of multicores. In the timing predictable embedded multicore architecture MERASA, the inter-task interference delay suffered by a Hard Real-time Task (HRT) can be bounded by the number of cores. Although this method can simplify the Worst-Case Execution Time (WCET) estimation, the value of WCET is seriously overestimated. To obtain tighter WCET estimation, we propose a novel approach that reduces the inter-task interference delay by optimizing bank-to-core mapping in the multicore system with the interference-aware bus arbiter and the two-level partitioned cache. For this, we first analyze and compute the inter-task interference delays suffered by the HRTs running simultaneously, and then put forward the core-queue optimization method of bank-to-core mapping and design the optimizing algorithms with the minimum inter-task interference delay. Experimental results demonstrate that our approach can reduce inter-task interference delay and improve estimated WCET.