• DocumentCode
    3749740
  • Title

    A novel low-loss high-isolation DP5T SOI CMOS switch in MCM for multi-band applications

  • Author

    Zhihao Zhang;Junming Lin;Kai Yu;Shenbiao Zhang;Liang Huang;Gary Zhang

  • Author_Institution
    School of Information Engineering, Guangdong University of Technology, Guangzhou, 510006, China
  • Volume
    1
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A monolithic double-pole, five-throw (DP5T) band switch has been implemented and fabricated in a 180nm thick-film partially-depleted (PD) SOI CMOS technology for the cellular handset multi-band applications. To reduce the power dissipation and eliminate the interaction between charge pump and RF-core circuitry, a novel switch configuration without integrating the negative voltage generator (NVG) is presented. This structure also helps to improve the insertion loss (IL) and isolation performance by LC series resonance in the series and shunt branch, respectively. The switch occupies a small chip size of 1.3mm × 0.65mm and is provided in a compact multi-chip module (MCM) package. The measured results show that this switch achieves an IL of 0.37dB, isolation of 24.2dB, 2nd and 3rd harmonic of -55.2 and -60.9dBm with a 28dBm input power at 900MHz. At 1900MHz, an IL of 0.53dB, isolation of >32.5dB, 2nd and 3rd harmonic of -50.7 and -53.7dBm with a 28dBm input power are obtained. Also, this switch exhibits a very low dc current consumption of 24.2uA, which make it very suitable for battery-operated applications.
  • Keywords
    "Switches","Switching circuits","Radio frequency","CMOS integrated circuits","Logic gates","Insertion loss","CMOS technology"
  • Publisher
    ieee
  • Conference_Titel
    Microwave Conference (APMC), 2015 Asia-Pacific
  • Print_ISBN
    978-1-4799-8765-8
  • Type

    conf

  • DOI
    10.1109/APMC.2015.7411811
  • Filename
    7411811