A 3.3 V 10 bit current-mode folding and interpolating CMOS A/D converter using an arithmetic functionality

Author

Chung, Jin-Won ; Yu, Hwa-Yeal ; Oh, Se-Hoon ; Yoon, Kwang-sub

Author_Institution

Dept. of Electron. Eng., Inha Univ., Inchon, South Korea

Volume

2

fYear

2000

fDate

2000

Firstpage

660

Abstract

A low power 10 bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3 V. The proposed ADC is implemented by a 0.6 μm n-well CMOS double poly/three metal process. The simulation result shows a differential nonlinearity (DNL) of -0.5 LSB, an integral nonlinearity (INL) of -1.0 LSB

Keywords

CMOS integrated circuits; analogue-digital conversion; current-mode circuits; interpolation; low-power electronics; 0.6 micron; 10 bit; 3.3 V; arithmetic folding block; current-mode folding-and-interpolating CMOS analog-to-digital converter; differential nonlinearity; folding amplifier; folding rate; integral nonfinearity; low-power design; n-well CMOS double poly/three metal process; Analog-digital conversion; CMOS process; CMOS technology; Circuits; Digital arithmetic; Digital signal processing chips; Frequency; Power dissipation; Signal processing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.952843

Filename

952843