Synchronization and delay estimation with sub-tick resolution

We consider the problem of clock synchronization between a pair of nodes using round-trip communication where only the initiating node collects time stamps, and where no time stamps are exchanged. These time stamps are the current timer values at the event of transmission or reception of a signal. Traditionally, the timer is modeled by a continuous function, i.e. as affine clock in case of asynchronism in clock skew and clock phase. In this work we deviate from the traditional model and propose a discrete-valued clock model, which is motivated by observations from real hardware. Employing the clock model allows us to find a new signaling model for round-trip time measurements, which enables us to simultaneously estimate clock skew, clock phase and propagation delay with a resolution below one clock tick period. Hence, we set a first step towards enabling high timing resolution with limited clock hardware.