Low power design of a word-level finite field multiplier using Reordered Normal Basis

A low power design for a finite field multiplier in F2m using Reordered Normal Basis (RNB) is presented. The main building block of the multiplier has been designed in domino logic. The basic idea is to reduce the contention between the keeper transistor and the pull-down network utilizing a new keeper control design to reduce the power dissipation. Simulation results in 65nm CMOS technology show that the proposed design offers 23.5% less power consumption compared to the previously presented design and 5% less than the static CMOS equivalent using the same basis while preserving the maximum operating speed of the dynamic design with almost no silicon area overhead.