Area efficient backprojection computation with reduced floating-point word width for SAR image formation

The widths of data words in digital processors have a direct impact on area in application-specific ICs (ASICs) and FPGAs. Circuit area impacts energy dissipation per workload and chip cost. Floating-point exponent and mantissa widths are independently varied for the seven major computational blocks of an airborne synthetic aperture radar (SAR) engine. The circuit area in 65 nm CMOS and the PSNR and SSIM metrics are found for 572 design points. With word-width reductions of 46.9-79.7%, images with a 0.99 SSIM are created with imperceptible image quality degradation and a 1.9-11.4× area reduction.