Compensating for sneak currents in multi-level crosspoint resistive memories

Crosspoint architectures for ReRAM offer highei density, power efficiency, and endurance than most other emerging memory technologies, but they suffer sneak currents thai cause significant write and read noise. Existing solutions limil the array size to ensure that the resulting noise falls within the margin between resistance levels but this might not be possible for MLC ReRAM memories. This paper builds a simple analytic model for the voltage drop and sneak currents in MLC-ReRAM arrays as a form of inter-cell-interference and proposes two techniques to minimize the resulting BER: spreading modulation and distribution shaping.