Efficient implementation of the filter bank based on FPGA

A hardware-efficient method of the poly-phase filter bank is introduced in this paper, and a filter bank with 16-fold decimation factor and 32 data paths based on the FPGA is presented. The Single-MAC FIR filters and the IFFT module based on the switch-cascade architecture are used in this design, a fact which can improve the system clock frequency and also shrink hardware logic resources greatly. The result indicated that the method is a high-efficient and the lowest cost for hardware implementation of the filter bank.