Energy Aware Synthesis of Application Kernels Expressed in Functional Languages on a Coarse Grained Composable Reconfigurable Array

With transistor energy efficiency not scaling at the same rate as transistor density and frequency, CMOS technology has hit a utilization wall, whereby large portions of the chip remain under clocked. To improve performance, while keeping power dissipation at a realistic level, future computing devices will consist of heterogeneous application specific accelerators. The accelerators have to be synthesised from high level specifications and will be specialized for related classes of application kernels. In this paper we explore synthesizing application kernels expressed as functions, on a coarse grained compos able reconfigurable array (CGCRA). The CGCRA consists of a set of reconfigurable data-paths called Hyper Cells, each of which can either compute an individual kernel, or can be composed together to compute a larger kernel. The proposed synthesis approach takes kernels expressed in a functional language, applies a sequence of well known program transformations, explores trade-offs between throughput and energy, and realizes the kernels on the CGCRA.