A Reliable Digitally Synthesizable Linear Drop-out Regulator Design for 14nm SOC

In Digital Linear Dropout (Digital LDO) implementation for System-On-Chips (SOC), the power gates operate in triode region and are distributed in bank structure. With wide dropout, the current distribution in the power gate bank turns out to be the key challenge. The proposed work presents a methodology/algorithm to distribute the current flowing through the bank of a digital LDO uniformly in a 14nm SOC implementation. This minimizes the chances of possible hotspot and ensures reliability for the SOC.