Modeling and characterization of hot-carrier stress degradation in power MOSFETs

Many applications require devices that are capable of handling voltages well in excess of the low voltage CMOS supply. Both high-voltage (20 to 100 V) and high current (2 to 3 A) output drivers are used within automotive, display drivers, paper media, digital media, and telecommunication applications. In addition, for cost and reliability reasons, there is a continuous trend for integrating power-handling transistors in the low-voltage CMOS process instead of using discrete devices. Hence, the so-called ?Smart Power? technologies are now proposed by almost all of the foundries, with platforms incorporating high performance power devices at a wide range of operating voltages. The lateral double-diffused MOS (LDMOS) transistor with shallow-trench isolation (STI) is the device of choice to achieve voltage and current capability integrated in the basic CMOS processes. The electrical characteristics of the STI-based LDMOS transistors will be reviewed over an extended range of operating conditions. The high electric-field regime will be explained to the purpose of investigating the effects on the electrical safe operating area (SOA) and device reliability under hot-carrier stress (HCS) conditions. The HCS degradation phenomena in this kind of transistors are strongly related to the specific nature of the device: the current flows laterally and close to the Si/SiO2 interface in all the regions. Hence the degradation probability is expected to be large, and the presence of the thick oxide in the drift region is the main reason for a limited HCS SOA. A review of the HCS physics-based modelling will be addressed to the purpose of understanding the degradation kinetics and mechanisms. TCAD simulations of HCS degradation will be finally shown to explain the HCS effects on a wide range of biases and temperatures.