An Optimized HPWL Model for VLSI Analytical Placement

In VLSI physical design, placement is an important stage. Analytical placer minimizes the half-perimeter wire lengh (HPWL) of the circuit as an objective function to place blocks optimally in the chip. This paper introduces a new smooth recursive model for HPWL function which can be used inside the analytical placers. The proposed model is more accurate than widely used log-sum-exponent (LSE)[9], weighted average (WA)[3] and ABSWL[7] models. The error upper bound of new approximation is also tightest among the existing wire length models. When deployed inside placement engine NUPlacer[1], it shows reduction in wire lengh by 12.3%, 10% and 3% on ISPD 2005 placement benchmarks compared to LSE, WA and ABSWL models respectively.