Implementation of reversible logic gates using adiabatic logic

In recent years, VLSI designers are more concerned about power minimization of digital circuits and in this field the reversible logic design has emerged as one of the powerful tool due to its low power consumption feature. Adiabatic logic is also an attractive solution for energy minimization. In this paper, we have combined both the adiabatic and reversible logic. The basic reversible logic gates FEYNMAN and TOFFOLI gates based on ECRL, 2PASCL and CMOS logics are evaluated on CADENCE VIRTUOSO EDA tool using UMC 180 nm technology. Simulation results show that 2PASCL adiabatic logic is better in terms of power dissipation than ECRL and CMOS in the range of 10MHz-100MHz.