Accurate analysis of settling error in CDS integrator based sigma delta modulators

This paper proposes an accurate analysis of the settling error in a Correlated Double Sampling (CDS) Integrator. This analysis is done in time domain and its MATLAB (M type) file implementation is directly applicable to the faster design implementation of Switched Capacitor (SC) based Sigma Delta (ΣΔ) Modulators. The analysis of settling error is done during the integration and sampling phase of a CDS Integrator. Validation of the proposed analytical model is done via extensive behavioral and transistor level simulations of a SC based Second Order ΣΔ Modulator employing a CDS integrator, in MATLAB and HSPICE, respectively, with Tower 0.18 μm process model parameters. The simulations were performed at two different values of modulator sampling frequency of 655 KHz and 5.24 MHz. The simulation results show a close agreement between the HSPICE simulations and proposed analytical model.