DocumentCode
3765287
Title
Spatial computing using Null Convention Logic
Author
Kashfia Haque;Conrad Jakob;Renuka Sovani;Paul Beckett
Author_Institution
School of Electrical & Computer Engineering, RMIT University
fYear
2015
Firstpage
106
Lastpage
109
Abstract
We present the design and organization of an homogeneous asynchronous bit-level array based on Null Convention Logic. A bit element (bel) array represents a bit-level hybrid processor that exhibits both Spatial and Temporal computing characteristics. The bit elements are organized in a 2D grid, with eight-way connectivity. Programs represented as Directed Acyclic Graphs can be mapped to the array either fully statically or with a small level of element reuse (dynamic mapping).
Keywords
"Field programmable gate arrays","Logic gates","Clocks","Encoding","Computers","Computer architecture","Organizations"
Publisher
ieee
Conference_Titel
Electrical and Computer Engineering (WIECON-ECE), 2015 IEEE International WIE Conference on
Type
conf
DOI
10.1109/WIECON-ECE.2015.7444010
Filename
7444010
Link To Document