Leakage current reduction in finfet based 6T SRAM cell for minimizing power dissipation in nanoscale memories

The power consumption of high performance integrated circuits has increased significantly with technology scaling. Higher power consumption shortens the battery lifetime of portable devices. Furthermore, the increased power consumption poses limitation on the continued technology scaling due to the associated higher power density. In this paper, the sources of power consumption are identified and modeled. Implementation of various techniques and the proposed technique for reducing total leakage current for low power SRAM cell is presented. It is observed in the paper that the total leakage current and power dissipation of the proposed technique is minimized to 52.89 fA and 4.75 nW respectively. Simulations have been performed on Cadence virtuoso 45 nm technologies.