An area efficient Q-format multiplier with high performance for digital processing applications

There has always been a quest going on for improving the performance of the multiplier as it is the key component in determining the performance of the digital signal processor. The Q-format multiplier implemented with Urdhva Triyagbhyam sutra of Vedic mathematics proved to be faster and area efficient. Yet, a further quest for increasing the performance of the Q-format multiplier resulted in the outcome of this paper. This paper presents a novel method using Booth encoding towards generation of reduced number of partial products and redundant binary adder for adding these partial products for implementation of 64 bit Q-format signed multiplier which substantially improved the performance by 22.60%, area reduced by 19.20%. This method has also been implemented for 16 bit and 32 bit multipliers along with 64 bit Q-format signed multiplier using Booth encoding and RB addition in VHDL targeted towards Xilinx FPGA Virtex-7 and results compared with those obtained by using Vedic Urdhva Triyagbhyam Sutra with CLA and found to have significant improvement in performance.