DocumentCode
3768163
Title
Performance analysis of ADMA on bus based SoC-survey
Author
N Narmadha;V Mithya
Author_Institution
Karpagam college of Engineering, Coimbatore, India
fYear
2015
Firstpage
1
Lastpage
4
Abstract
Power models are at the heart of high level estimation methods for industrial, efficient evaluation of system on-chip bus protocol termed as MSBUS-DMA. The efficiency of DMA had less throughput, performance level also less in while transferring data during block transfer mode. The main issue of DMA extra hardware cost and extra code size, and complexity of the software are high. In this paper to improve bandwidth, low power, low cost and in order to reduce complexity advanced direct memory access controller (ADMA) is proposed methodology. To estimate bus performance in various analytical models including area, power, entire performance level, speed of data while transmitting, time consumption, bandwidth as achieves high performance in ADMA technique based on bus based system on-chip. First of all ensure the routing technique for MS-ADMA.
Keywords
"Protocols","System-on-chip","Computer architecture","Bandwidth","Wires","Estimation","Complexity theory"
Publisher
ieee
Conference_Titel
Green Engineering and Technologies (IC-GET), 2015 Online International Conference on
Type
conf
DOI
10.1109/GET.2015.7453789
Filename
7453789
Link To Document