Design and implementation of ASIC verification platform for the SAR algorithm

This paper presents a method of the implementation of a verification platform. The platform is applied to an ASIC chip designed for the key algorithm of SAR signal processing. The design is a complicated process and the chip function is computationally burdensome, thus the verification is difficult. Balancing the competing demands for efficiency, quality, time and cost, the verification platform is carefully designed using the Verilog language, with Synopsys VCS-MX2009 adopted. The experimental results show that the design errors of timing and anti-protocols have been exactly checked out and the verification coverage reaches 100% at last. The platform possesses satisfying characteristics such as high performance, fine configurability, flexibility and expansibility.