DocumentCode
3769404
Title
Design of a large point FFT processor with configurable transform length
Author
Yu Xie;Yang-kai Feng;Chen Yang;Yi-zhuang Xie;He Chen
Author_Institution
Beijing Key laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing, China, Shanghai institute of satellite engineering
fYear
2015
Firstpage
1
Lastpage
5
Abstract
In this paper, a scheme of a large point FFT processor with configurable transform length is proposed. To achieve a pipelined structure, the proposed scheme is designed by Radix-2 decimation-in-frequency (DIF) FFT algorithm with Single-path Delay Feedback (SDF) architecture. A prototype is implemented on Xilinx Virtex-7 XC7VX690T FPGA, which can compute 16~128K FFT at a speed as high as 350MHZ.This scheme is superior to existing technologies, due to its ability to process a continuous-flow input sequence and its prospect for real-time, configurable transform length applications.
Publisher
iet
Conference_Titel
Radar Conference 2015, IET International
Print_ISBN
978-1-78561-038-7
Type
conf
DOI
10.1049/cp.2015.1335
Filename
7455557
Link To Document