Theory study and implementation of configurable ECC on RRAM memory

Resistive random access memory (RRAM) has been recognized as one of the most promising candidates for next generation non-volatile memory due to its simple structure and excellent scalability. However, poor reliability is a serious issue for RRAM memory applications. To improve the reliability and endurance, many researchers changed the cell material, process and structure. Here, in this paper, we propose an error-correction code (ECC) method to improve RRAM chip reliability. BCH code is adopted in our configurable and adaptive-rate error correction scheme that the ECC correction capability changes when the error mode changes.